Genesys CTI User Forum
Genesys CTI User Forum => Genesys CTI Technical Discussion => Topic started by: AladdinAssisi on March 31, 2021, 12:18:48 PM
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I am trying to model an SRD (Step Recovery Diode) to simulate the performance of a monocycle pulse generator as described in the Agilent Application Note "Nonlinear Modeling of Step Recovery Diode using Verilog-A".
But I cannot include the Verilog-A model with GENESYS.
Can anyone tell me how to do it?
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Google? :D :D :D
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Where is your answer?
I am one of the oldest Genesys users, since it was created by the great engineer Randy Rhea. I have been designing with Genesys since 1994 till now.
I am asking a serious question and you are just laughing.
How do you call yourself the "Genesys Guru"?
Where is the solution of my simulation problem?
Dr. Eng. Aladdin Assisi
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Hi, Aladdin,
I believe this is another Genesys System... this is the Genesys CTI forum and not Electronics Design
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Look like an interesting read ...
Filter Synthesis Using Genesys S/Filter (Artech House Microwave Library (Hardcover))
ISBN-13: 978-1608078028
ISBN-10: 1608078027
Craig
B.Eng (First class Honours), CEng, MIEE
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Thank you
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[quote author=hsujdik link=topic=11975.msg53829#msg53829 date=1617280229]
I believe this is another Genesys System... this is the Genesys CTI forum and not Electronics Design
[/quote]
LOL